Name: An Introduction to Risc v. "Reduced Instruction set Computer" Processor (en Inglés)
SKU: 62656615
Price: 36.18 USD
Availability: InStock
Author: Arpita Patel
ISBN: 9783389028421

portada An Introduction to Risc v. "Reduced Instruction set Computer" Processor (en Inglés)

An Introduction to Risc v. "Reduced Instruction set Computer" Processor (en Inglés)

Formato

Libro Físico

Editorial

Grin Verlag

Autor

Arpita Patel

Idioma

Inglés

N° páginas

Encuadernación

Tapa Blanda

ISBN13

9783389028421

An Introduction to Risc v. "Reduced Instruction set Computer" Processor (en Inglés)

Arpita Patel (Autor) · Grin Verlag · Tapa Blanda

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Reseña del libro "An Introduction to Risc v. "Reduced Instruction set Computer" Processor (en Inglés)"

Document from the year 2024 in the subject Computer Science, grade: A, language: English, abstract: RISC-V, an open-source Instruction Set Architecture (ISA), has become a significant performer in the realm of computer architecture, challenging traditional proprietary designs and opening the doors for innovation and customization. Initially in this work, RISC-V's historical evolution, its architecture, including its design concepts, instruction set, register file and implementations, were understood through a literature survey.A comprehensive literature survey is conducted on various variants of RISC-V family and their applications, which include lowering total costs, speeding up processor execution, consuming less power, and creating a more manageable and compact versions of the original architecture. The study includes a thorough analysis of several RISC-V variations. According to review of the literature, the 32-bit biRISC-V processor core is the newest member of the RISC-V family and using superscalar dual issue design to increase processor overall throughput.