Name: Cost-effective Methods for High-speed Nanometer CMOS VLSI Design. Interconnect and Circuits. 2nd Edition (en Inglés)
SKU: 65458685
Price: 66.79 USD
Availability: InStock
Author: Charbel Akl
ISBN: 9786208480622

portada Cost-effective Methods for High-speed Nanometer CMOS VLSI Design. Interconnect and Circuits. 2nd Edition (en Inglés)

Cost-effective Methods for High-speed Nanometer CMOS VLSI Design. Interconnect and Circuits. 2nd Edition (en Inglés)

Formato

Libro Físico

Editorial

LAP LAMBERT Academic Publishing

Autor

Charbel Akl

Año

2025

Idioma

Inglés

N° páginas

132

Encuadernación

Tapa Blanda

Dimensiones

22x15 cm

ISBN13

9786208480622

Cost-effective Methods for High-speed Nanometer CMOS VLSI Design. Interconnect and Circuits. 2nd Edition (en Inglés)

Charbel Akl (Autor) · LAP LAMBERT Academic Publishing · Tapa Blanda

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Reseña del libro "Cost-effective Methods for High-speed Nanometer CMOS VLSI Design. Interconnect and Circuits. 2nd Edition (en Inglés)"

The semiconductor industry has been following Moore’s law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.