Name: multicore systems on-chip: practical hardware/software design, 2nd edition (en Inglés)
SKU: 24804823
Price: 65.07 USD
Availability: InStock
Author: Ben Abdallah, Abderazek
ISBN: 9789491216916

portada multicore systems on-chip: practical hardware/software design, 2nd edition (en Inglés)

multicore systems on-chip: practical hardware/software design, 2nd edition (en Inglés)

Formato

Libro Físico

Autor

Abderazek Ben Abdallah

Editorial

Atlantis Press

Año

2013

Idioma

Inglés

N° páginas

273

Encuadernación

Tapa Dura

Dimensiones

23.4x16x2.3 cm

Peso

0.54 kg.

ISBN

9491216910

ISBN13

9789491216916

Categorías

Hardware (o soporte físico del ordenador)
Arquitectura y diseño lógico de ordenadores

multicore systems on-chip: practical hardware/software design, 2nd edition (en Inglés)

Abderazek Ben Abdallah (Autor) · Atlantis Press · Tapa Dura

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Reseña del libro "multicore systems on-chip: practical hardware/software design, 2nd edition (en Inglés)"

System on chips designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing. The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowing to reduce the voltage on each core. Because dynamic power is proportional to the frequency and to the square of the voltage, we get a big gain, even though we may have more cores running. As more and more cores are integrated into these designs to share the ever increasing processing load, the main challenges lie in efficient memory hierarchy, scalable system interconnect, new programming paradigms, and efficient integration methodology for connecting such heterogeneous cores into a single system capable of leveraging their individual flexibility. Current design methods tend toward mixed HW/SW co-designs targeting multicore systems on-chip for specific applications. To decide on the lowest cost mix of cores, designers must iteratively map the device's functionality to a particular HW/SW partition and target architectures. In addition, to connect the heterogeneous cores, the architecture requires high performance complex communication architectures and efficient communication protocols, such as hierarchical bus, point-to-point connection, or Network-on-Chip. Software development also becomes far more complex due to the difficulties in breaking a single processing task into multiple parts that can be processed separately and then reassembled later. This reflects the fact that certain processor jobs cannot be easily parallelized to run concurrently on multiple processing cores and that load balancing between processing cores - especially heterogeneous cores - is very difficult.