portada IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection (en Inglés)

IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection (en Inglés)

Formato

Libro Físico

Autor

Khaled Salah Mohamed

Editorial

Springer

Idioma

Inglés

N° páginas

154

Encuadernación

Tapa Blanda

Dimensiones

23.4x15.6x0.9 cm

Peso

0.24 kg.

ISBN13

9783319373584

N° edición

Categorías

Electrónica: circuitos y componentes
Ordenadores centrales («mainframes») y miniordenadores
Arquitectura y diseño lógico de ordenadores

IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection (en Inglés)

Khaled Salah Mohamed (Autor) · Springer · Tapa Blanda

Libro Nuevo Importado

Envío: 16 a 23 días háb.

$ 108.24$ 54.12

-50%

Costos de importación incluídos en el precio ✅

Libro Nuevo

Quedan más de 100 unidades

$ 54.12

Llega entre el 15 Sep y el 28 Sep a Quito, Pichincha. Seleccionar ubicación

Agregar a lista de deseos

Reseña del libro "IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection (en Inglés)"

This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including those associated with many of the most common memory cores, controller IPs and system-on-chip (SoC) buses. Readers will also benefit from the author's practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain. A SoC case study is presented to compare traditional verification with the new verification methodologies.Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection; Introduce a deep introduction for Verilog for both implementation and verification point of view. Demonstrates how to use IP in applications such as memory controllers and SoC buses.Describes a new verification methodology called bug localization;Presents a novel scan-chain methodology for RTL debugging;Enables readers to employ UVM methodology in straightforward, practical terms.