portada Systemverilog for Hardware Description: Rtl Design and Verification (en Inglés)

Systemverilog for Hardware Description: Rtl Design and Verification (en Inglés)

Formato

Libro Físico

Autor

Vaibbhav Taraate

Editorial

Springer

Año

2020

Idioma

Inglés

N° páginas

252

Encuadernación

Tapa Dura

Dimensiones

23.4x15.6x1.8 cm

Peso

0.56 kg.

ISBN13

9789811544040

N° edición

Categorías

Electrónica: circuitos y componentes
Hardware (o soporte físico del ordenador)

Systemverilog for Hardware Description: Rtl Design and Verification (en Inglés)

Vaibbhav Taraate (Autor) · Springer · Tapa Dura

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Reseña del libro "Systemverilog for Hardware Description: Rtl Design and Verification (en Inglés)"

This book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC.